10 Gbps RapidIO in MicroTCA for wireless networking

As wireless networks move to services requiring higher data rates and more services per subscriber, equipment vendors must optimize capital expenditures when deploying new services such as WiMAX, evolved Wideband Code Division Multiple Access (CDMA), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), which is the Chinese 3G standard, or 3G Long Term Evolution (LTE).

Between the conflicting requirements for more data per subscriber, more subscribers per line card, lower cost per supported subscriber, ease of deployment, and equipment cost structures, equipment vendors have had to press hard on standards bodies, silicon vendors, and system vendors to deliver high-performance turnkey solutions. Short design cycles pressure system vendors into leveraging standards wherever possible.

The higher data rates in WiMAX, eWDCMA, TD-SCDMA, and 3G LTE lead to, among other things, increased processing requirements. What with OFDM PHY processing for those standards that use Orthogonal Frequency Domain Multiplexing as well as the Verterbi and Turbo decoding processing loads, the ìon cardî connectivity is pushing 10 Gbps for actual data rates. Moreover, as the number of subscribers grows, not only are 10 Gbps links required on baseband cards between processing, but 10 Gbps is also used on backplanes.

The MicroTCA form factor offers an ideal standards-based solution for low-cost basestation development. The AMC.4 specification offers RapidIO 10 Gbps connectivity on primary lanes, making the job of system vendors easier than ever. The RapidIO interconnect shines as the interconnect of choice for both onboard and backplane interconnect.

System architecture using MicroTCA and the AMC.4

PICMG defines MicroTCA as an equipment form factor targeted for telecom and enterprise networking applications. It offers many of the benefits of the AdvancedTCA specification (PICMG 3.0) in a much smaller form factor, making it suitable for applications, such as wireless basestations, where performance must be delivered at low cost. The MicroTCA specification calls for backplane bandwidth ranging from 1 to 12+ Gbps, ensuring its sufficient inter-card capacity for most of todayís and tomorrowís wireless applications.

A MicroTCA system as defined by PICMG is a collection of interconnected elements consisting of at least one AdvancedMC (AMC) card, at least one MicroTCA Carrier Hub (MCH), and the interconnect, power, cooling, and mechanical resources needed to support them. PICMGís AMC series of specifications defines the lane mapping on AMC cards to support PCI Express (PCIe), RapidIO, and Ethernet backplanes. The AMC.4 specification (RapidIO) in a MicroTCA system enables wireless baseband designers to quickly develop systems leveraging up to 10 Gbps of actual data rate.

Figure 1 shows a typical architecture for a wireless baseband system. In the context of MicroTCA, the Radio Frequency, Network Interface, and Baseband Cards are all AMC form factor. They are connected across the backplane with an MCH, in this case leveraging RapidIO switching for the data plane and optionally for the control plane. The RF TDM data from multiple antennae may be combined into one stream and passed to the MCH, where a Serial RapidIO switch multicasts the same stream to all the baseband cards.

Figure 1 (click graphic to zoom by 3.5x)

The baseband cards extract the actual data or voice signals out of the combined stream, leveraging the processing capabilities of FPGAs, DSPs, and microprocessors to implement multiple tasks, including OFDMA PHY processing as well as Verterbi and Turbo decoding.

RapidIO in a MicroTCA backplane

Until recently, off-the-shelf solutions with RapidIO were not readily available for MicroTCA backplanes. Now multiple MicroTCA carrier cards, such as the Tundra Tsi578 MSM (MicroTCA Switching Module) shown in Figure 2, are available from vendors, including Mercury Computer Systems and N.AT., leveraging RapidIO switches to offer connectivity between AMC cards and the carrier hub. These cards support up to 12 RapidIO AMCs each, connected at up to 10 Gbps of actual data rate, leveraging the AMC.4 specification, as well as front panel 10 Gbps RapidIO. In the context of wireless systems, we will see how this can be useful especially in the case of real estate limited AMC cards where the functionality of one baseband card may have to be split over two, thus requiring the transmission of high data rates between cards.

This is an even greater concern in WiMAX and LTE systems that need RapidIOís x4 mode to transmit 10 Gbps of actual data between processing elements. Moreover, when actual user data rates start to exceed 100 Mbps each, the aggregate load created by numerous users is quite significant. To accommodate the multigigabit data rates, systems can be easily designed using 10 Gbps, which overprovisions the links today for the expected traffic. As traffic grows, the same architecture can continue to support the links by leveraging the QoS and priority management features available in RapidIO switches and endpoints. All of this makes 10 Gbps RapidIO ideal for chip-to-chip (onboard) interconnect as well as board-to-board (across the backplane) in a MicroTCA chassis.

MicroTCA backplanes and signal integrity

When designing systems with 10 Gbps of data going across serial links on a backplane, signal quality attenuates due to trace lengths. The attenuation is more dramatic for high-frequency harmonics that also get phase shifted. The signal integrity issues from the MCH card differ for each one of the AMC cards due to the length of each trace.

The outcome is that the signal that is transmitted by a switch on one AMC card and received at the MCH card can often be severely compromised, to the point that the eye diagram is barely visible.

To achieve a clean eye diagram, the first step can involve amplifying the transmitted signal. However this approach only increases overall system power consumption (which is at a premium in the MicroTCA chassis) while also elevating the noise floor. Moreover, it does not solve the problem of phase shifting of high-frequency signals over the length of the backplane link.

A feature available in RapidIO switches that allows the designer to tune the pre-emphasis on the transmitted signal, which in effect amplifies and phase shifts the high-frequency harmonics to account for the effects of the transmission line, results in a clean eye diagram at the receiver. This feature must be available on a per port basis on the switch, given that each port connects to a link of a different length with differing impedance and noise characteristics. On the receive side switches also have the ability to perform receive equalization, also on a per port basis. In this case the received signal is taken and ìconditionedî to amplify high-frequency harmonics and phase shift those harmonics to account for some of the negative impact of the link.

An AMC form factor card, the Serial RapidIO Signal Analyzer from Tundra Semiconductor (see Figure 3), is an example of a tool that enables system designers to adjust MicroTCA chassis switches for high quality board-to-board high-speed signals. This solution includes software that is placed in each AMC slot and used to analyze the quality of the eye.

The card can be used inside MicroTCA chassis and in standalone mode. One of the biggest values is seeing the quality of the eye diagram as actually received inside the die of the switch after it has traversed the balls and packaging. Conventional solutions only allow the user to see the eye before the package is traversed, by placing down a scope outside of the actual switchís package. The accompanying On Chip Scope Software (OCS) can run on a PC and communicate to the hardware via USB to set transmit and receive parameters.

10 Gbps interprocessor connectivity on baseband cards

As bandwidth grows in wireless baseband to 100 Mbps and more per user, the processing load on DSPs, processors, and FPGAs becomes increasingly onerous. System vendors put silicon in place to implement system-level software and firmware and not to terminate an interconnect protocol between processing elements. Moreover, in voice and video applications low latency is a key attribute for system-level performance, which is further impacted by involving the software stack to terminate the interconnect protocol. Using RapidIO, the DSPs and processors can terminate the interconnect in silicon without eating into processor cycles and at the same time minimize latency.

RapidIO provides a three-layer protocol that is completely terminated in hardware, with zero software intervention, which makes it ideal for embedded applications. Processor resources are thereby allocated completely to system-level application code, and latency is minimized as a result of eliminating the need to involve software in terminating a software stack.

We need to look at the actual data rates for various embedded system interconnect protocols. In next generation wireless systems, the actual data bandwidth needed is significantly higher than in 3G applications as the data rate per subscriber grows beyond 100 Mbps in LTE. Available bandwidth on links between processing elements should ideally be up to 10 Gbps, providing some overprovisioning, while at the same time leaving room for growth leveraging RapidIOís various QoS features.

When studying the available bandwidth the key attribute to focus on is the actual data rate of the protocol, when 8b/10b encoding and header overhead is removed. When examining strictly data payload, RapidIO compares favorably to other protocols not optimized for the embedded computing space (Figure 4).

RapidIO excels when shipping data in small packets, which is typically the case for embedded solutions, where latency and congestion in endpoints associated with long packets is undesirable. Even with short packets of up to 64 bytes an actual efficiency of 67 percent is achieved, while at 256 byte PDUs, over 90 percent efficiency is achieved. This is a substantial advantage compared to using PCI Express or Gigabit Ethernet. While Ethernet shines in WAN implementations, the features that make it strong there make it a weaker choice in MicroTCA systems. Ethernetís high tolerance for packet loss, lack of flow control, and lack of automated hardware recovery for bit errors make it ineffective for 10 Gbps data interconnect between processing elements on baseband cards in a MicroTCA chassis.

Available hardware today

Implementing baseband cards in MicroTCA has never been easier than it is today. There are a number of off-the-shelf options featuring FPGAs, processors, and DSPs all leveraging RapidIO for local interconnect as well as RapidIO for backplane connectivity leveraging the AMC.4 spec. With a number of new RapidIO enabled multicore DSPs from TI and Freescale coming to the market in the past year, the ecosystem has expanded substantially. In essence, they use a mix of DSPs and FPGAs with x4 RapidIO connectivity at 3.125 Gbaud to offer 10 Gbps of actual data rate connectivity between processing elements. These AMC solutions can be used to implement out-of-the-box baseband processing. The solutions can be single card AMCs or a base plus a mezzanine, given the space limitations of the AMC form factor.

The beauty of a RapidIO based implementation is that it offers flexible partitioning between different processing elements in a baseband card, while ensuring minimal latency and no processing overhead when passing data between elements. Figure 5 shows a logical block diagram of elements used in a wireless baseband line card.

Moving to fourth generation networks, whether it is LTE or WiMAX, vendors are generally performing the Orthogonal Frequency Division Multiplexing Access (OFDMA) protocol in FPGAs or ASICs. The wireless operator and vendor community has moved toward an emerging consensus that OFDMA is more robust, more spectrum-efficient, and more amenable to supporting Multiple Antenna Systems (MAS) than CDMA. Various AMC solutions featuring onboard FPGAs work well for this implementation. In addition to the onboard FPGAs, DSPs with specific accelerators for Verterbi and Turbo Decode are then used to complete processing tasks. Embedded processors are often used to perform MAC processing tasks, while also being leveraged for system bring up and control plane functions. All of these elements are optimally connected using RapidIO switches. Today, numerous AMCs offer solutions with different I/O features, FPGAs, and DSP selection to optimize out-of-the-box wireless baseband card design. They include but are not limited to

• Commagility AMC-D4F1 with quad Texas Instruments TCI6482 DSPs8144AMC-S with quad MSC8144 multicore DSP
• Commagility AMC 6487 with triple Texas Instruments TCI6487 DSPs
• Mercury MTI203 WiMAX AMC
• Texas Instruments TCI6484 EVM with dual Texas Instruments TCI6484
• Tundra Tsi620 MultiProtocol RapidIO Switching Card

Conclusion

Over the past few years the ecosystem for developing wireless basestations using MicroTCA and RapidIO has substantially expanded. Today there are off-the-shelf components readily available that allow System OEMs to develop basestations using the MicroTCA form factor while leveraging the true 10 Gbps connectivity of RapidIO. With the move to WiMAX and LTE developments, 10 Gbps links between processing elements on AMCs and from AMC to AMC across the backplane becomes increasingly important. With todayís AMC solutions and switch cards along with tools for backplane link characterization, the building blocks are commercially available to get to market quickly. System OEMs can then add their value by implementing firmware and software for the application-level functionality that requires OFDMA PHY processing, MAC layer processing, Turbo Decode, and Verterbi processing in the available processing elements offered on the AMCs.

Devashish Paul is Tundraís Product Marketing Manager for Serial RapidIO switching products. Over the past 10 years he has run product lines in the semiconductor and networking industry at companies like Semiconductor Insights, Solidum Systems, Mosaid Semiconductor, and Nortel. Prior to his commercial career, he had a successful eight- year career in the Canadian Air Force where he was a Systems Engineer for airborne radar systems for both the CP-140 and the F-18 Program. Devashish has a Masters in Electrical Engineering in Digital Signal Processing and an MBA from the University of Ottawa. His Bachelorís degree in Electrical Engineering is from the Royal Military College of Canada.