PICMG's Interconnect Channel Characterization Committee -- bringing the embedded industry up to speed
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Looking at the current market for open specification equipment, a common trend emerges - the customer is driving the demand for higher performance. This drive not only relates to the performance of the silicon, but also to the interconnect, the fabric that links these blades and modules together. The requirement to develop higher-speed interconnects has put designers under increasing pressure to create solutions that meet more and more stringent requirements. At the turn of the century, the single Gigabit Ethernet (GbE) interconnect was considered challenging. However, by last year the standard performance was the 10 GbE XAUI (4 lanes of 2.5 GbE combined to create a 10 GbE channel), and now in 2009 the 40 GbE systems (4 lanes of 10 GbE running at 12.5 Gbps SERDES combined to create a 40 GbE channel) are being released to the market by companies like Emerson Network Power. Based on this development timeline, 100 GbE solutions are not far away.
While people expect devices to "plug and play" together, increases in backplane speeds cause many factors to come into play. Speed may be thought of as acting as the recruiter for a high-performance team. The higher the frequencies involved, the more the signals create problems that require solutions in layout, material, and many other aspects. These differences magnify – with regard to silicon, connectors, and backplanes – with these higher-speed solutions. As a result, the interoperability aspects of these open solutions, where equipment from many vendors teams up, have to be considered carefully.
The knowledge to drive system architecture
Recognizing these developments as part of the natural evolution of the market, PICMG formed the Interconnect Channel Characterization (ICC) committee in 2007 to develop a new specification. The specification is designed to establish ground rules and definitions for characterizing the transmission, reflection, and crosstalk performance of backplane and mezzanine carrier interconnects. This information is being developed to help system designers and integrators predict more effective solutions in the scope of increasing the capabilities of the interconnect. Knowing the performance of a channel before designing or integrating a solution around it gives designers the means to drive the system architecture. For example, the committee looked at the aspects of channel performance characterization and subsequently created a common methodology to represent it in a standard form.
The initial framework of the specification allows multiple solutions to be tested in a standard way. There are currently a number of variations of this framework, such as Figure 1, which shows reference plane designations for board-backplane-board topology such as AdvancedTCA and the relationship to different combinations of mezzanine, carrier, blade, backplane, and the like, with the channel definitions being constant for all.
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Figure 1: (click graphic to zoom by 1.4x) |
Once created, this framework allowed the committee to focus its efforts on more crucial aspects of the problems. When the initial statement of work was written, it was expected that differential s-parameters would be used to define the channel performance. These measurements would be standardized by using one of the frameworks, such as in Figure 1, to allow combination and comparison.
Aspects of the ongoing work have been focused on the test equipment required to provide an accurate and repeatable set of values to accurately reflect channel characteristics. Currently, the specification suggests a number of solutions in the area of testing fixtures and connectors. These solutions are included to provide consistency and standardization of measurements, as well as the experience of the committee in measuring these characteristics.
Of course, once you have the model/parameters for the channel there is a need to deal with the information gained. The specification examines the techniques and definitions associated with the analysis of the results, again to provide consistency, and to aid the designers using the solution.
Conclusion
The work being carried out by the ICC committee represents a strong addition to the PICMG specification family. It has paved the way for the next generation of specifications with a baseline framework for defining new high-performance channels. The ICC committee is also working closely with the AdvancedTCA 3.1 R2.0 committee to suggest improvements and understand the requirements of the specifications. This work is ongoing at the time of this writing.
Finally, the specification is currently in draft 0.59, with a prospective release in the late 2009 time frame.
Note: Figure 1 is used with permission of the PICMG ICC committee. The figure and the specification discussed here are at the draft level and can be changed without notice. Do not design using the information discussed here.
Stuart Jamieson is Director, Industry Relations/Architect for the Embedded Computing business of Emerson Network Power and the editor on the PICMG MicroTCA.3 and the Interconnect Channel Committee, as well as introduction author for MicroTCA.1.For more information, contact Stuart at Stuart.Jamieson@Emerson.com
