Signal integrity in high-speed connectors – the need for more accurate channel simulation and characterization measurement
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Channel characterization has become a major Signal Integrity (SI) issue, driving connector manufacturers of high-speed components to provide comprehensive and empirical SI test data that their equipment performs as specified for the targeted application.
The need for speed is everywhere. The Internet Protocol (IP) has become tremendously important for combining data, voice, and video in the same data stream. Different networks such as the Internet Protocol Multimedia Subsystem (IMS), Voice over Internet Protocol (VoIP), Mobile VoIP, and others use the same protocol for these data packages, a phenomenon referred to as converging networks. Mobile data services require a higher aggregate bandwidth for network elements found in base stations, radio network controllers, and core networks, which have to accommodate this increased data traffic.
What started as a gradual trend to higher bit rates accelerated dramatically in 2004 with the introduction by Intel of the PCI Express standard. Following this lead, the majority of chip-to-chip connection standards underwent an architectural shift from parallel buses to SERerializer/DEserializer (SERDES) links, called lanes.
With the IP-based infrastructure in place, new standards, including IEEE 802.3ap, evolved for higher data rates, especially for Ethernet over the backplane assembly. However other standards like RapidIO and PCI Express also address higher data rates. Typical data rates are in the range of 3.125 gigabaud (Gbaud) per lane and some interconnects already support 10.3125 Gbaud lane rates. Different protocols are used for the data transport, and each link technology has different requirements for the channel. However, some limits and electrical requirements are defined in the relevant specification.
While IEEE 802.3ap is being adopted for new designs, the Ethernet task force is developing IEEE 802.3ba for 40 Gbps and 100 Gbps for future data networks. AdvancedTCA, for instance, the largest specification effort in the history of the PCI Standard, targets next-generation carrier grade communications equipment needs. This series of specifications incorporates the latest trends in high-speed interconnect technologies and next-generation processors, promising improved reliability and availability.
But these large bit rate increases come at a cost. At multigigabit per second data rates with channel flight times longer than a bit period, signal integrity is compromised. High-speed analog effects can impair the signal quality and degrade the Bit Error Rate (BER) of the link. To ensure optimum performance of high-speed connectors, simulation and characterization analysis needs to be performed – comprehensively and empirically – to establish and adhere to uniform standards.
Cleaner signals are key
Signal integrity concerns high-speed circuit design and enabling cleaner signals to travel the designs. Cleaner signals, in turn, allow engineers to identify and minimize sources of distortion in data transmission, which could otherwise disrupt timing of the digital logic.
The ability to effectively transmit a signal is related to the ratio of signal to interference that is presented to the receiver. Many challenges must be addressed in developing a system where any channel can support transmitting a signal serially at 10 Gbps. At multigigabit per second data rates, link designers must consider reflections at impedance changes, noise induced by densely packed neighboring connections (cross talk), and high-frequency attenuation. Other significant issues of concern for signal integrity that can plague modern digital products and interfere with the detection of the output signal are ringing, ground bounce, and power supply noise.
Comprehensive signal integrity tests of connectors in backplane applications have been conducted by HARTING, as well as concurrently supporting standardization subcommittees within PICMG and with- in the Open Base Station Architecture Initiative (OBSAI). Appendix 69B of the IEEE 802.3ap standard, which defines the informative limits of the channel, defines a confidence level, but this is neither normative nor a guarantee that the channel works or does not work without a BER failure.
It is obviously very challenging to define normative parameters, especially for lane rates beyond 3.125 Gbaud, due to the need for signal conditioning. Separating the channel with defined reference points helps to isolate specific areas of the transmission path. However, cascading the signal elements later requires careful calibration and de-embedding techniques, especially between the reference transition points.
The PICMG Interconnect Channel Characterization Committee (ICCC) is developing a document with ground rules and definitions for channel characterization. Taking it a step further and considering the signal propagation path from the cable connector makes the challenge the ICCC is facing even more difficult. For example, 10 Gbps Small Form Factor Pluggable (SFP+) modules and hosts are well defined within the latest SFF draft specifications with specific electrical requirements and test procedures.
While focusing mainly on the physical layer, the transmission of signals between transmitter and receiver can be from chip-to-chip on the same board or chip-to-chip between different boards. When the signal is between different boards, the physical connection could be a PCB, cable, or connector. Figure 1 illustrates a data transmission path with an arbitrary assignment of different connector types.
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Figure 1: A data transmission path with an arbitrary assignment of different connector types. (click graphic to zoom by 1.9x) |
PCB and cable signal traces carry much more current than their on-chip counterparts. This larger current induces cross talk primarily in a magnetic, or inductive, mode, as opposed to a capacitive mode. To combat this cross talk, digital PCB designers must remain acutely aware of not only the intended signal path for every signal, but also the path of returning signal current for every signal. The signal itself and its returning signal current path are equally capable of generating induc-tive crosstalk.
The measurement of the signal between the chips is not trivial, and the test fixture and measurement procedure have a strong impact on the results. Comprehensive documentation with all details of the test fixture and instrument settings is mandatory for the interpretation, reproducibility, and comparison of the results.
The backplane channel in IEEE 802.3ap is defined between Transmitter and Receiver test points TP1 and TP4 (see Figure 2, the IEEE 802.3ap interconnect reference model).
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Figure 2: The IEEE 802.3ap interconnect reference model. (click graphic to zoom by 1.9x) |
Channel test and simulation parameters
TP1 and TP4 are reference test points in IEEE 802.3ap. Informative channel parameters between these two test points are defined in Annex 69B for 1000BASE-KX at 1.25 Gbaud, 10GBASE-KX4 at 3.125 Gbaud, and 10GBASE-KR at 10.3125 Gbaud. Table 1 lists the test parameters, and Figure 3 shows the channel limits of a measured backplane.
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Figure 3: The channel limits of a measured backplane. (click graphic to zoom by 1.8x) |
At these new multigigabit per second bit rates, the bit period is shorter than the flight time and echoes of previous pulses can arrive at the receiver on top of the main pulse and corrupt it. In signal integrity engineering this is called an eye closure – a reference to the clutter in the center of a type of oscilloscope trace called an eye diagram – representing the results of a simulation driven by a long, multicycle sequence, which superimposes each bit period over the top of others.
In IEEE 802.3ap the test parameters are informative only, and the results do not guarantee that the channel finally works without bit error rates. Other standards like RapidIO or OIF-CEI-02.0 agreement use tools such as Stateye for compliance testing. (Figure 4 shows a Stateye eye run.) However, the correct measurement of the data is a strong concern in the industry.
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| Figure 4: A Stateye eye run. |
A characterization challenge
The characterization of the passive channel is not trivial. The data transmission through the channel (refer again to Figure 1) is very complicated. Coax connectors, typically 2.4 mm/2.92 mm/3.5 mm, terminate the measurement instrument’s cables (Figure 5). Access to the component edges is difficult, requiring four measurement test fixtures. The test fixture has a strong impact on the results. An error correction is required to remove these effects from the measurement data. To avoid the rise time degradations and reflections due to the launch connector transition, the use of a high-precision probe such as the HARTING Probe Station is recommended.
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| Figure 5: Coax connectors, typically 2.4 mm/2.92 mm/3.5 mm, terminate a measurement instrument’s cables. |
The launch of the connectors for the instrument cables (most likely SMA termination) to the PCB has to be very smooth. Figure 6 depicts a connector launch with SMA termination. A 3D dynamic field solver optimizes the transition from the board mount coax connector to the PCB trace. The production process of the test cards is very critical, and special attention has to be paid to make sure the impedance match of the test fixture, including the connector transition, is very accurate.
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Figure 6: A connector launch with SMA termination. (click graphic to zoom by 1.7x) |
Scattering (S)-Parameters are measured with a Multiport Vector Network Analyzer. The S-Parameters can capture the reflection and transmission from junctions in backplanes. It’s also important to control the isolation between signals in order to avoid interference from adjacent channels.
The data can also be gained with a time domain instrument, when time domain to frequency domain transformation is required. While selecting the best software tools and measurement equipment is important for performing channel characterization, the operator’s skill in using the software and test equipment properly is the key to accurate results.
High-speed connection must-haves
As systems are developed to continually support greater high-speed capacities, the design, simulation, measurement, and analysis of connectors to optimize channel signal integrity will need to be even more exacting.
The requirements demanded of high-frequency and high-speed connections are considerable. They must be compact, able to withstand hard mechanical knocks, and compensate for tolerances between the daughter card and the backplane. What’s more, they must not cause any significant signal reflections or attenuation and must guarantee a reliable contact for at least 15 years.
Such tried and tested connection standards should be expected, and demanded, by both component manufacturers and those that integrate them. Only in this way can a truly functional mega-gigabit system that supports computing, storage, control, media, and packets become widely functional.
markus.witte@harting.com
HARTING North America
www.HARTING.com
