CompactPCI moves ahead
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Dog days? More like dogged pursuit of a number of markets for CompactPCI, and success as CompactPCI demonstrates its ability to adapt – check out the mil-areo app described in the Global Technology column this month.
Most successful computer open standards, if they are to remain viable, adapt to changes in technology. The best expand their capabilities while maintaining a high degree of backwards compatibility. This leverages existing product offerings and reduces the cost of upgrades. CompactPCI, which has been around for 15 years now, has continued to evolve to improve performance and add new features. The original spec supported the 33 MHz, 32-bit parallel PCI bus. This was then expanded to 66 MHz, 64-bit PCI.
By the year 2000, parallel buses like PCI were being supplanted by higher-speed switched serial buses. They were popping up like weeds and were simply too numerous for all to survive. Some were chip-to-chip interconnects, while others were intended to interconnect boards at the system level. The most popular system-level interconnect, Ethernet, just kept getting faster, cheaper, and better. In 2001 a PICMG technical committee headed up by John Peters from Performance Technologies developed a specification that allowed boards in a CompactPCI system to communicate via Ethernet over the backplane. This was the industry’s first switched serial fabric standard, and it is still widely used. In 2005 PCI Express was added as a backplane interconnect in the CompactPCI Express specification.
CompactPCI is still a large and healthy business, and it is being upgraded again. The PICMG 2.30 specification, which should be ratified shortly, adds modern interfaces such as SATA, USB, and PCI Express to the backplane. It does so by using a higher speed but mechanically compatible connector in the J2 position and specifies a consistent method for using the User I/O pins for these new interfaces. For even higher speed signaling, a follow-on specification known as CompactPCI Plus is under develop-ment. This uses a high-speed differential connector known as AirMax. It sacrifices some backward compatibility, but provides very high performance for those that need it. Manfred Schmitz from MEN Mikro, along with Roland Nuiten of 3M, give us a good overview of these two specs in their article in this issue. For those interested in the details of the connector, Charlie Staley from 3M explains how the new connectoring for PICMG 2.30 works in a separate article.
Over the years, CompactPCI has moved far beyond its original markets and is now quite popular in the military and avionics markets. This month our European correspondent Hermann Strass tells us how Pilatus, a high-end Swiss airplane manufacturer, uses conduction-cooled CompactPCI in its newest training aircraft, the PC-21.
Switching gears, multiple computing cores are replacing the gigahertz race in high-end processors. There is a fair amount of confusion about how to write software that takes advantage of multicore and multithreaded CPUs. I talked to Jim St. Leger from Intel to get some basic knowledge about the issues surrounding these machines, and I hope you find the interview (online at advancedtca-systems.com) educational.
Rounding out this issue, Sven Freudenfeld from Kontron gives us an update on the state of the AdvancedMC world, Venkataraman Prasannan from RadiSys explains the importance of modeling and systems integration for the AdvancedTCA marketplace, and Curt Schwaderer dives into deep packet inspection. Enjoy.
Joe Pavlat, Editorial Director


